The invention relates to a semiconductor device with a semiconductor body made of silicon which is provided at a surface with a first MOS transistor with an insulated gate of polycrystalline or amorphous silicon and with a non-volatile programmable memory element in the form of a second MOS transistor with an electrically floating gate of polycrystalline or amorphous silicon and with a control electrode of polycrystalline or amorphous silicon situated above the floating gate and electrically insulated therefrom. The invention also relates to a method of manufacturing a semiconductor device with a semiconductor body made of silicon which is provided at a surface with a first MOS transistor with an insulated gate of polycrystalline or amorphous silicon and with a non-volatile programmable memory element in the form of a second MOS transistor with an electrically floating gate of polycrystalline or amorphous silicon and with a control electrode of polycrystalline or amorphous silicon situated above the floating gate and electrically insulated therefrom.
The term "poly" will be used hereinafter for short; It should be borne in mind that this term covers not only polycrystalline silicon but also amorphous silicon.
Such a semiconductor device and a method of manufacturing this semiconductor device are known inter alia from Applicant's U.S. Pat. No. 5,395,778.
The memory element together with a large number of similar elements will usually form part of a non-volatile memory which is familiar under the designations EEPROM or (flash) EPROM. This memory may be of a stand-alone type, in which case the semiconductor device mainly comprises the memory and the peripheral electronics necessary for it. Said first MOS transistor may then be formed by a transistor from the periphery, but also by a selection transistor which forms a memory cell together with a memory transistor. In alternative embodiments for which the invention is of particular, though not exclusive importance, the memory may be embedded, the semiconductor device being an integrated signal processing circuit with a built-in non-volatile memory. A standard CMOS process is mostly used for the manufacture of such a circuit, supplemented with a few additional process steps for the memory in the signal processing portion (called logic hereinafter). As is generally known, information is written in the form of electric charge which is stored on the floating gate and which defines the threshold voltage of the transistor. The information may be read in that it is ascertained whether the transistor is conducting or not, given a suitable voltage at the control electrode.
The cited patent U.S. Pat. No. 5,395,778 describes a process in which the floating gate and the control electrode are provided in a split-poly process where the poly deposition necessary for forming the logic gates is carried out in two steps. In the first step, a first partial layer for the logic is formed as well as the poly layer of the floating gate, which is subsequently covered with an interpoly dielectric. In the second step, the remainder of the poly layer is provided for the logic gates while at the same time a poly layer for the control electrode is formed above the poly, layer of the floating gate, electrically insulated therefrom by the interpoly dielectric.
The poly layer in the logic has a greater thickness than the poly layer of the control electrode in the memory in this process, which leads to drawbacks under some circumstances. Thus it may be necessary to carry out an overetching in the memory portion if the control electrode and the insulated gates of the logic are simultaneously defined and etched. Another drawback may arise when the sides of the control electrodes and of the insulated gates are both provided with spacers through deposition and etching-back of an oxide layer. It is possible in this case that the oxide layer in the memory portion is etched back too far relatively as a result of the thickness difference between the poly layers. This in its turn may lead to short-circuits (bridging) when subsequently the source and drain zones and the gates are provided with silicide contacts in a salicide process known per se.